1. Field of the Invention
The present invention relates generally to a random access memory device and, more particularly, to a nonvolatile ferroelectric random access memory device with a segmented plate line and a method for driving a plate line segment.
2. Description of Related Art
Random access memory devices are well known in the art. One type of random access memory is a ferroelectric random access memory (FRAM), which employs a ferroelectric capacitor as the storage element for each memory cell. A FRAM stores a logic state based on the electrical polarization of the corresponding ferroelectric capacitor. When a sufficient voltage potential difference (i.e., above the switching threshold or coercive voltage level) is applied to the plates of the ferroelectric capacitor, the ferroelectric material of the capacitor is polarized in the direction of the electric field.
Typically, one plate of a ferroelectric capacitor is coupled to a bit line via an access transistor and the other plate is coupled to a plate line. For example, FIG. 1 illustrates a FRAM circuit having a conventional segmented plate line scheme. As shown, a global plate line (GPL) drives a number of segmented plate lines (PL00 through PLNN) via access transistors, a word line decoder (WL DEC) drives a number of word lines (WL0 through WLN), and a sense amplifier/column decoder (labeled Sense Amplifier and Column Decoder Circuit) is coupled to the ferroelectric capacitors via corresponding bit lines and access transistors.
In standby, the word lines and the segmented plate lines are at a low voltage level. During operation, one word line activates one row of the segmented plate lines which is driven by the global plate line. A drawback of this scheme is that a segmented plate line pull-down circuit (one of which is circled in FIG. 1 and labeled PLPD) is required, which increases the loading of the word line and the overall size of the circuitry (i.e., chip area). Thus, there is a need for an improved FRAM device having fewer components and having word lines with less loading.
Another FRAM circuit is shown in FIG. 2 having a segmented plate line scheme as disclosed in U.S. Pat. No. 6,201,727, which is incorporated herein by reference in its entirety. As shown in FIG. 2 along with the respective timing diagram shown in FIG. 3, in standby, all segmented plate lines (PLS0 through PLSm) are coupled to ground by driving a signal on PRCHG control lines high. During access, a signal is driven high on an SEL control line, and a word line (one of WL0 through WLm) is activated, resulting in the selected word line charging one of the local segmented plate lines (one of PLS0 through PLSm). One drawback of this scheme is that the extent of the loading of the word line and the plate lines can limit the voltage level ramp-up, which in turn can limit device operation speed. Thus, the operational speed can be limited. As a result, there is a need for an improved FRAM device having reduced loading of the word lines and plate lines and, further, having memory cells with improved access time and cycle time.
The present invention seeks to meet these needs of the prior art by providing, in accordance with one aspect, random access memory (RAM) devices with reduced loading on the word lines and plate lines. The reduced loading of the word lines and plate lines can enable increased voltage level ramp-up times on the word lines and plate lines without area penalty.
The present invention further seeks to address the prior art needs by providing a method of operating a random access memory device wherein plate lines are charged by a local plate line decoder or other circuit, instead of being charged directly by the row decoder. Moreover, pull-down circuits are not connected, so the area penalty is small. Consequently, by operation of the row decoder selecting local plate lines instead of actually charging them, access times and cycle times of the random access memory device can be increased.
To achieve these and other advantages and in accordance with a purpose of the present invention, as embodied and broadly described herein, the invention provides random access memory devices and methods for operating the devices. For example, in accordance with one aspect of the present invention, a random access memory device includes a number of memory cells, with word lines, plate lines, and bit lines coupled to the memory cells. A switch, controlled by a word line, couples one end of the plate line to a first global plate line, while another switch, controlled by a second global plate line, couples the one end of the plate line to a reference voltage. The plate lines are charged by the first global plate line, which improves operational speed of the device, reduces loading of the word lines, and improves the access time and cycle time of the memory cells.
In accordance with another aspect of the present invention, a random access memory device includes a plurality of memory cells, a word line, a plate line, a plurality of bit lines, a first global plate line, a second global plate line, a first switch circuit, and a second switch circuit. The word line, plate line, and bit lines are coupled to the memory cells, and each of the memory cells is arranged at an intersection of the word line and a corresponding bit line. The first switch circuit, responsive to a voltage potential asserted on the word line, couples one end of the plate line to the first global plate line. The second switch circuit, responsive to a voltage potential asserted on the second global plate line, couples the one end of the plate line (and the first switch circuit) to a reference voltage.
In accordance with yet another aspect of the present invention, a random access memory device includes a memory cell array, a plurality of word lines and a row decoder. The row decoder selects one of the word lines and activates the selected word line. The memory cell array is divided into a plurality of memory blocks, with each of the memory blocks including a plurality of memory cells, a plurality of plate line segments, a plurality of bit lines, a first global plate line, a second global plate line, a local plate line decoder, a plurality of first switch circuits, and a plurality of second switch circuits. In the memory block, the memory cells are arranged at intersections of the word lines and the bit lines. The plate line segments couple to the memory cells, and one end of each of the plate line segments is coupled to a corresponding one of the first switch circuits and the second switch circuits. The first switch circuits further are coupled to the first global plate line, and the second switch circuits are further coupled to reference voltages. In this case, each of the first switch circuits is controlled by a corresponding word line, and each of the second switch circuits is controlled by the second global plate line.
Furthermore, in accordance with another aspect of the present invention, a method for driving a plate line in a random access memory device is disclosed. The method includes asserting a first voltage potential on a word line to switch a first switch circuit off to decouple a plate line from a first global plate line; asserting a second voltage potential on a second global plate line to switch a second switch circuit on to charge the plate line with a reference voltage; asserting a third voltage potential on the word line to switch the first switch circuit on so as to couple the plate line to the first global plate line; asserting a fourth voltage potential on the second global plate line to switch the second switch circuit off so as to decouple the plate line from the reference voltage; and asserting a signal on the first global plate line such that the plate line has a plate line voltage.
In each of the foregoing aspects, the present invention provides a switch that is controlled by a word line and that couples one end of a plate line to a global plate line, and further provides another switch that is controlled by a second global plate line and that couples the one end of the plate line to a reference voltage. The plate lines are charged by the first global plate line, which can improve operational speed of the device, reduce loading of the word lines, and improve the access time and cycle time of the memory cells.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art.
Additional advantages and aspects of the present invention are apparent in the following detailed description and claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.